PSRAM Controller

Power consumption is more and more critical in many applications, such as battery-powered equipments, very low power applications and other fields like automotive, military, etc … Thus, choosing and using a very low power external memory such as a PSRAM (Pseudo-Static RAM) memory can be a very interesting solution (less than 40 mA during burst read operations @ 104 MHz) ALSE has developed a very compact and efficient controller that can be easily integrated in any FPGA project.

Main Technical Features

  • High-Performance Controller supporting Burst Mode for Read/Write transfers, to get optimized transfer speed and minimal switch fabric overhead.
  • Memory Operating Frequency > 100 MHz, depending on FPGA and Memory speed grades, and (more marginally) on the customer PCB characteristics.
  • 32bits Slave Interface (Avalon-MM based) with Burst support.
    Typically, the Controller will serve a Master that can be an Altera Nios II CPU (32bits), with or without caches, with or without Burst mode.
    A hardware master (DMA) is of course also possible.
  • Support of different PSRAM memory standards (e.g : Micron CellularRam 1.0/1.5/2.0)
  • Support of PSRAM memory with Multiplexed address/data bus
  • Versatile.
    This IP can be used in all FPGA devices (Intel / Altera, Xilinx, Lattice, MicroSemi / Actel) having internal memory blocks.
  • Easy integration using Altera Qsys, or manually.
  • Provided with sophisticated SDC Timing Constraints, Hardware Tester Reference Designs, etc…

Examples of supported Memories

  • Micron MT45W2MW16BGB
  • Micron MT45W4MW16BCGB
  • ISSI 66WVD4M16ALL
  • etc …

If your specific Flash is not supported yet, ALSE can easily add its support to this list.

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