ChipBridge (Chip-To-Chip)

This IP is ideal to control a lot of peripherals from a centralized high-end (Master) FPGA (or ASIC) ! Connecting and controlling peripherals from the Master directly is typically difficult and inefficient : lack of support for 3.3V I/Os, level translators and ESD protections required, difficulty to modify the main FPGA to adapt to changes in the peripherals, Electrical and Safety issues, PCB routing, and real estate issues…

Using a single transceiver and two pairs of signals, ChipBridge allows to extend the AXI4 mapping to an external FPGA while maintaining good access performance (latency) and bandwidth. The Slave FPGA can be low cost, low power, and robust.

ChipBridge is a “Chip-To-Chip” AXI4 connectivity solution allowing to displace peripherals to an external FPGA. This allows a Master System On Chip FPGA (or ASIC), typically with embedded processor(s), to transparently access peripherals connected to a Slave FPGA. In other words, ChipBridge can extend the AXI4 interconnect outside the main chip.

The first ChipBridge IP Core was developed on Lattice CertusPro-NX FPGAs using a high-speed (10G) transceiver through an ALSE Aurora Light 64B/66B IP for the physical interconnect. However, other physical streaming links (like LVDS) can be used.

Likewise this IP core targets mainly Lattice FPGAs but is compatible with most other FPGAs.

The Datasheet is below.

Don’t hesitate to contact us if you want more information on this IP.

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