High-Speed JPEG Video Encoder

This is a “dual-core” version of our standard JPEG encoder.
It is still compact enough and efficient to fit in a very small low cost FPGA while allowing real time compression at higher resolutions than Full-HD at 60fps.
It has an option to generate a video stream optimized for GPU decoding ! This is a unique feature on the market, now tested and used on high-end commercial products.
This IP does not require any processor nor any external memory.

Purpose

This “Dual-Core” High-Speed Baseline JPEG Encoder (Compression) core is capable of encoding video on-the-fly while producing standard JPEG compressed format. Its “Dual-core” architecture doubles the compression speed as compared to our standard baseline JPEG Encoder. The use of JPEG compression allows using very small FPGAs without external memory, leading to very economical systems, and our dual-core architecture allows high resolution and frame rates compression on low cost FPGAs.

Architecture

ALSE HighSpeed (dual-core) JPEG Encoder

Easy to use

Our core is compact and implements standard interfaces, so it can be used easily either as a standalone block, or as part of a Platform Designer system (or equivalent).

Again : it does not require any embedded processor. It is small and efficient enough to fit easily in low cost and small FPGAs, like in the Altera Cyclone and Agilex3 families, or the Lattice FPGA families (eg ECP3, ECP5, Certus-NX, CertusPro-NX, Crosslink-NX, Mach-XO5 etc) or the Microchip FPGAs (Igloo 2 or Polarfire).

It fits (indeed) very well in higher end families (Altera Agilex5 or Agilex7, Lattice Avant-X and Avant_G etc), thus offering the capability to support high resolutions and frame rates. Our simulation environment can be helpful to develop and the application that includes the JPEG encoder.

Main Technical characteristics

  • Speed and Area-Optimized encoder engine
  • Suitable for both still image and real-time video compression.
  • 8 bits (byte) Streaming output interface with Backpressure. Easy to connect to the ALSE Ethernet communication engine for example. Output format is 8x8 YUV Blocks (4:2:2).
  • Option to generate a video stream optimized for multi-thread GPU decoding !
  • Supports any image resolution up to 64k x 64k.
  • Standard Huffman table.
  • Dynamically configurable Quantization tables (up to 8 tables) for multiple levels of compression and quality.
  • Dynamic choice of compression level (can be adjusted automatically).
  • Can be easily integrated in a complete video system using the ALSE “Block to Raster” module, a Memory Frame Buffer and a Video Output Controller (RGB outputs for VGA, LCD; YUV BT656, etc … )
  • Versatile. This IP can be used in all FPGA devices (internal memory blocks must indeed be available).
  • Compact.
  • Fast : excellent Fmax on all FPGA families.
  • First-class Technical Support (E-mail and Telephone, extended CET hours).
  • Customization to specific needs is possible.
  • Verification Environment with advanced test benches.

Best in class

Some ALSE IPs also exist in the competition, JPEG Codec is in this case. However, our IP offers unique characteristics and advantages.

  • More compact.
  • More efficient than the competition.
  • Faster (better Fmax).
  • Dual-engine version
  • Optimized for multi-thread decoding (GPU) -encoder, option-.

Demos available

We have many demos created for many FPGA boards.

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