Aurora 8B/10B IP Core

The ALSE Aurora 8B/10B IP Core is a lightweight, high-speed, and low latency serial protocol suitable for chip-to-chip, board-to-board and backplane applications using Transceivers.
For Xilinx users, Aurora is available as a Xilinx Logicore IP.
Our IP makes Aurora 8B/10B available to other FPGAs (and potentially ASICs), including Intel-FPGAs, but also Lattice (Certus Pro NX) and Microchip (PolarFire).
Therefore, IP provides an efficient way to interconnect a Xilinx FPGA (for example) with an Intel or Lattice or Microchip FPGA, or any other chip (ASIC, ASSP, etc …) using the Aurora 8B/10B public protocol.
It can even be used to interconnect two FPGAs from the same vendor together, in replacement of other proprietary or complex High-Speed Serial protocols (like Serial Lite III or PCIExpress).
The Figure below shows a typical application of the IP :

Aurora Typical Application
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Main Aurora 8B/10B Protocol Features supported

  • Full-Duplex and Simplex Tx Operations.
  • Simplex Rx Operation supported
  • Currently demonstrated at up to 6.6 Gbps (Gigabits per seconds) per Transceiver lane.
    Higher bitrates are possible, depending on the Device Transceiver characteristics (max 8b/10b Encoder/Decoder Bitrate).
  • Up to 16 Transceiver lanes.
  • Framing and Streaming interface.
  • Payload Data User Frames (PDU)
  • User Flow Control (UFC).
  • Native Flow Control (NFC), in immediate and completion mode.
  • Additional CRC for PDU Frames
  • 8b/10b Encoding / Decoding.
  • Clock Compensation sequence generation.
  • Per lane polarity inversion and skew compensation.
  • User datapath depending on number of lanes and 16bits/32bits mode per Transceiver lane. Examples :
    -> in a x1 /32bits configuration, the user datapath is 32bits.
    -> in a x4 /16bits configuration, the user datapath is 64bits.
    -> in a x4 /32bits configuration, the user datapath is 128bits.

Note : we have also an Aurora 64B/66B IP core available for higher speeds !

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Other Technical Features

  • Practically all Intel-FPGAs are supported : Arria 10, Stratix 10, Stratix V, Arria V, Cyclone V. Note that Agilex FPGAs are preferably using our Aurora 64B/66B IP. _We support also other FPGA vendors (including Lattice and Microsemi/Microchip).
  • AXI streaming / Avalon-ST compatible for User interfaces (PDU, NFC, UFC)
  • Very low FPGA resource usage : typically less than 1000 ALMs / 2 Memory Blocks for a Full IP in a x1 (1 lane) configuration
  • Provided with SDC Timing Constraints and QIP file for easy integration in Platform Designer.
  • Hardware Tester Reference Designs
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Examples of existing Hardware Tester Reference Designs

  • CycloneV Clovis/AVDB -> Xilinx Virtex6 ML605, x1 - 3.125Gbps
  • CycloneV Clovis/AVDB -> Xilinx Virtex7 VC707, x1 - 3.125Gbps
  • Arria10 Attila -> Xilinx Virtex7 VC707, x1 - 6.25Gbps
  • Arria10 Achilles -> Arria10 Attila, x4 - 6.25Gbps
  • Stratix10 GX Dev Kit -> Arria10 Achilles, x4 - 6.25Gbps
  • Lattice Certus Pro Nx development kit
  • Microchip Polarfire development kit
  • etc …

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Document download

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