Purpose

Our Baseline JPEG Encoder (Compression) core is capable of encoding video on-the-fly while producing standard JPEG compressed format. More efficient compression formats exist (we have also a 2D wavelet CODEC) and even inter-frame compression with motion estimation, but these techniques are much more bulky. JPEG allows using very small FPGAs without using external memory, leading to very economical systems.

Easy to use

Our core is compact and implements standard interfaces, so it can be used easily either as a standalone block, or as part of a Qsys system. Again : it does not require any embedded processor. It is small and efficient enough to fit easily in low cost and small FPGAs, like in the Intel Cyclone III, Cyclone IV or Cyclone V families.

The core can be used as stand-alone block or with Qsys, with or without the Altera Video IP suite (“VIP”).

Our simulation environment can be helpful to develop and the application that includes the JPEG encoder.

This core has been used (with the corresponding JPEG Decoder) in a very successful consumer product.

This IP core is also used in many Demos and Reference Designs that are available with ALSE’s AVDB Video board. In many cases, purchasing an AVDB board to develop or to prototype the application will make a lot of sense.

Main Technical characteristics

• Speed and Area-Optimized encoder engine suitable for both still image and real-time video compression.
• 8 bits (byte) Streaming output interface with Backpressure. Easy to connect to the ALSE Ethernet communication engine for example. Output format is 8x8 YUV Blocks (4:2:2).
• Supports any image resolution up to 64k x 64k.
• Suitable for still image and real-time video (streaming).
• The core can accept close to 1 pixel per clock cycle.
• Standard Huffman table.
• Dynamically configurable Quantization tables (up to 8 tables) for multiple levels of compression and quality.
• Dynamic choice of compression level (can be adjusted automatically).
• Can be easily integrated in a complete video system using the ALSE “Block to Raster” module, a Memory Frame Buffer and a Video Output Controller (RGB outputs for VGA, LCD; YUV BT656, etc … )
• Versatile. This IP can be used in all FPGA devices (internal memory blocks must be available).
• Compact. On an Altera Device, the area is typically less than 3,300 Logic Elements, 5 memory blocks (M9K) and 9 DSP18-bits (multipliers) are used.
• Fast : on an old Altera EP3C25F256C6 Cyclone III Device, the Encoder can run at more than 150 MHz.
• First-class Technical Support (E-mail and Telephone, extended CET hours).
• Customization to specific needs available.

Best in class

Some ALSE IPs also exist in the competition, JPEG Codec is in this case. However, our IP offers unique characteristics and advantages.

• More compact.
• More efficient than the competition.
• Faster.

Demos available

We have many demos created for several FPGA boards, including our AVDB Video Development Board.

Information available

A datasheet is available, but do not hesitate to contact us if you want more details.