LVDS (Low Voltage Differential Signalling) is a standard that uses two signals (a “pair”) to carry a value which is the (small) voltage difference between the two wires.
Typically, the voltage difference is small (0.4V eg) around a common mode voltage (1.2V eg).
LVDS pairs are terminated by a low impedance (100 Ohms eg) so each pair consumes a constant current of 3.5mA.
As a consequence, LVDS pairs can transport easily very high speed signals (above 1G) at low power, with simple and cheap wiring (twisted pairs cables, or microstrips on PCBs are typical).

Usual applications often use one pair to transport the base frequency (word) clock (50 MHz in our demo), and one or many more pairs to transport the high-speed serialized data at a factor usually between 7:1 and 10:1.

Video or image applications (like flat panel drivers or Camera links) often use a serialization factor of 7:1.
Our demo will use a 10:1 factor (500 Mbits/s).

This Application Note shows that it is very simple to create and test such a link, and we use one of the cheapest FPGA kits for this demo.

You can read all the details and the source code in the complete article below.