JESD204

JESD204 is the Data Converter Serial Interface standard that was created through the JEDEC committee, with the participation of all the industrial providers of high-speed ADC and DACs (including Ti, Analog Devices etc).

If you want to use High Speed ADCs or DACs in your project, you need an FPGA with transceivers and a JESD204 IP !

And ALSE has JESD204 IPs available for many FPGA families and vendors.

See our Reference Design documentation below.

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Purpose

The first purpose of JESD204 is to provide the ability to transfer reliably Data at very high speeds, using as few wires as possible. Obviously, these requirements lead to using HSSLs (High Speed Synchronous Serial Links) i.e. Transceivers (SERDESes) and pairs of wires for low voltage differential signalling.

Beyond Data transfer, JESD204 provides services allowing an extremely precise knowledge of the samples position in absolute time (synchronization and time stamping in particular) which is compulsory and very critical when signals are acquired through multiple ADCs or formed using multiple DACs.

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Principle

A JESD204B Interface involves Transceivers to transmit serially at very high speed parallel Data on one or several lanes. This is the PHY layer. It is based on the Transceivers of the FPGA you have selected.

The Link layer is the protocol (scrambling, encoding, character and lanes alignments, assembling…)

The transport layer deals with frames of data.

And in practice, a control & status registers interface will be available to monitor and control the IP.

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Versions

  • The first standard widely adopted was JESD204B in 2011 (based on 8/10 encoding, offering deterministic latency)
    To date, it is still the most used version.
  • JESD204C (based on 64/66 encoding) is becoming common for the latest converters.
  • And JESD204D is under way.
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Multiple Challenges

You may think that finding a working IP is the main challenge. While it may not be very simple to make the right choice, you would be wrong if you don’t anticipate the many other complex aspects of the task.

  • The JESD204B DACs, ADCs and support chips (like JESD204B Compliant PLLs) are extremely complex to parameterize and use. Just take a look at the LMK0482 PLL datasheet (128 pages) or the DAC38RF 147 pages.
  • Synchonization and dealing with latency can be challenging too.
  • For very high speed DACs & ADCs, there is another difficulty inside the FPGA to handle and process the extreme streams of data, often with multiple samples per beat.
  • If you have to deal with hardware and board design, with links up ti 12.5 Gb/s, there will be no room for the smallest error.
  • Dealing with transceivers is never trivial.

If you start struggling with your project involving JESD204B (or C), don’t hesitate to contact ALSE.

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